France

To address the increasingly challenging requirements of the RF front-end (RFFE) for 5G and also anticipated requirements for 6G, the 3D heterogeneous integration of GaN HEMT coupons on a RF-SOI technology is sought for combining the advantages of a high performance RF component and a capable Si based platform. Integration is performed at the transistor level rather than at a functional block level with conventional packaging methods. High performance RF passives, analogue, digital, and I/O functionality is performed by a 130nm RF-SOI technology with Cu and thick Cu metallurgy. GaN HEMT devices are instantiated as necessary to achieve design targets. Several examples of design innovation have been recently demonstrated by X-FAB including a 5.9-7.1GHz High-Linearity LNA, where the first stage cascode combines a HEMT and a Si NMOS exploiting higher output power and linearity of GaN. The second example is a SPST switch, where reduced insertion losses were observed in comparison to GaN on Si as a benefit of the integration method and also a significantly larger power handling capability than a Si counterpart. This discussion will include the present status and remarks on the future of this enabling technology.

ESSCIRC ESSDERC Educational Events

multi-technology wafer level integration for RFFE applications

rffe

rf-soi

heterogeneous integration

The IEEE Workshop on Wide Bandgap Power Devices & Applications (WiPDA) provides a forum for device scientists, circuit designers, & application engineers from the Power Electronics & Electron Devices Societies to share technology updates, research findings, experience & potential applications.

**Topics of interest**

* Heteroepitaxial & Bulk Materials Growth
* Gate Dielectrics & Surface Passivation
* Device Structures & Fabrication Techniques
* Device Characterization & Modeling
* Very-High Efficiency or Compact Converters
* Safe Operating Areas of Wide Bandgap Devices, Including Short Circuit, Spike, & Transient Tolerance
* Harsh Environment (High Temperature) Operation & Reliability
* Packaging Power Modules & ICs
* Hard-Switched & Soft-Switched Application Analysis
* Gate Drive & Other Auxiliary Circuits
* High-Performance Passive Components
* Applications in Renewable Energy & Energy Storage, Transportation, Industrial Drives, & Grid Power Systems
* Wide Band Gap System Design Philosophies & Strategies
* Radio Frequency (RF) GaN (New)
* Technology Roadmap of Wide Bandgap Including Devices, Applications and Packaging (New)

### Please select the button below to view and download the session papers. The Virtual Proceedings PDF can be downloaded [here.](https://drive.google.com/file/d/171y2_u63V-pc9-bC-eZgHLzJou2oCfST/view?usp=sharing)

[![](https://assets.underline.io/uploads/markdown_image/1/image/c8e1b0a2881d3bb0a75ece4761f43c9f.png)](https://drive.google.com/drive/folders/1GWEFLzH6K4aUBaJiBFJDw4x9sKLTl6-g?usp=sharing)


This event requires a registration to attend, please register [here](https://web.cvent.com/event/536cea3d-4c0d-4d50-8939-529979d80785/summary) to purchase a ticket. 

IEEE WiPDA 2021

The IEEE Workshop on Wide Bandgap Power Devices & Applications (WiPDA) provides a forum for device scientists, circuit designers, & application engineers from the Power Electronics & Electron Devices Societies to share technology updates, research findings, experience & potential applications.

technical paper

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021<br>
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021<br>
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021<br>
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021<br>
(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**

Please register for educational events at the following link: https://www.registerme.eu/event/esscirc-essderc-2021/

Please register for the ESSCIRC/ESSDERC Educational Events to join the event.

The Educational Events of ESSCIRC ESSDERC 2021. 

Design of 3D ICs is mainly done in separated design environments for each tier, assuming that communication channels between tiers are user-defined and fixed at the beginning of the design process1,2. Suitable for 3D stacking based on TSV or Hybrid Bonding technologies because of the low granularity of these 3D interconnect elements, this methodology becomes more difficult to apply to 3D sequential technologies once trying to integrate Monolithic Inter-tier Vias (MIV) with higher density (around 1.108 vias per mm2). In this paper, we describe a methodology to create a unified design environment, which includes several technologies attached to different tiers. Main advantage of this methodology is that designing a 3D circuit may no more require several design environments, thus simplifying simulations, verifications and layout finishing.

Merging PDKs to build a multi-process multi-tier 3D design environment

A 14-bits cyclic ADC is implemented in two-tier 3D sequential integration
(3DSI) multi-process technology. The ADC specifications are intended
for the daughter-payloads of the investigation of cusp irregularities (ICI) sounding
rocket series, i.e. small sensor platforms that are ejected in-flight to measure
plasma electron density in a cloud around the rocket. The two 3DSI processes
used are a 65nm SOI technology with 28nm shrink transistors in the top tier
and 28nm FDSOI as the bottom tier. This work aims to explore architectures
in a high-density interconnect 3D sequential integration process for area and
power reduction, exploiting fine-grained transistor placement as well as device
parameter optimization having the choice of two different CMOS technologies
for each individual device.

14-bits Cyclic ADC in 3D sequential multi-process Technology

This presentations deals with innovative approaches of 3D stacking Image sensors. Comparisons with conventionnal 3D vs sequential stacking is described.

Innovative Fine Pitch Architectures dedicated to Image Sensors: from Hybrid Bonding to 3D Sequential integration

The presentation is related to the EU-funded 3D-MUSE project where an extra layer of transistors is produced on top of a standard CMOS technology. Some readout circuits for radiation will be presented as well as how they can make use of several transistor layers. Examples are a multi-channel PMT, a thermal image sensor and a light radar. A simple TDC (Time to Digital Converter) will also be presented.

3D Integrated Circuits for Radiation Sensor Readout

In an industry wide consensus perpendicular spin-transfer-torque magnetic random-access memory (pSTT-MRAM) has matured to the memory of choice for replacing embedded FLASH solutions in the 2X nm technology nodes and beyond. However, especially this first entry point as a replacement for solder-reflow-capable eFLASH implies stringent requirements when it comes to high temperature data storage capabilities. In highly scaled pSTT-MRAM this demanding non-volatility can only be achieved by advanced free layer engineering. This energy barrier modulation needs to be carefully balanced in the boundary conditions of power consumption and endurance requirements. Sustaining and predicting this balance already at film-level or during patterning will be highly rewarding for the reliable manufacturing of this new technology. Here we present an early view on film-level and post-patterning magnetic metrology for embedded pSTT-MRAM.

Magnetic Metrology on Fully Integrated Embedded STT-MRAM

The architectural innovations of a new FPGA is presented.
The programmable Element, the routing structure and innovative switchboxes are explaned.

Novel Architecture for European FPGA

The modern world witnesses an ever-growing variety of consumer, home, automotive and industrial devices with network connectivity. 
Security is a crucial aspect in such systems and stakeholders will confirm that security constantly evolving. 
Therefore, NXP is very much involved in developing resilient, secure and trustworthy products that are a crucial building block for European data sovereignty. 
This results in the foundation that our customers use to build secure products.

In this presentation we will highlight the contributions of NXP Semiconductors Austria in the scope of IPCEI. 
This ranges from implementation security for high security products like Roots of Trust, 
over safe and secure battery management system for the green revolution as well as innovative 
application of technology for security use cases like Ultra-Wide-Band (UWB) radio for car access.

A connected world – Why security matters

5G standards effective deployment drives considerable technology challenges and implications on mobile devices design and requires innovative solutions to solve them. 
At the RF Front End Modules (FEM) level, the usage of new frequency bands, the complex use of the frequency bands (Carrier Aggregation, MIMO, QAM) and the coexistence with 4G networks are challenging the limits of existing acoustic filter technologies. 
A promising approach combining a thin single crystal LiTaO3 layer bonded on a Silicon substrate - so called Piezo On Insulator (POI) – together with the existing Surface Acoustic Wave (SAW) filter technology, enables to take advantage of guided waves that do not suffer from any radiation leakage. This SAW on POI approach will extend the use of the existing SAW technologies for higher performance integrated acoustic devices.
Triggered by the 5G filter market demand, the Smart CutTM technology has enabled high performance POI substrates supply chain in volume manufacturing, and paves the way to new design approaches for many applications beyond the Smartphone market.


Smart CutTM Piezo On Insulator (POI) substrates for high performance integrated acoustic devices

The IPCEI program at GF includes innovation along all technology readiness levels (TRLs). One example for very low TRL is the Reconficurable FET based on Schottky Barriers, close to 22FDX-processing. It enables camouflaging circuits for security applications, by e.g. providing NAND or NOR type cells, that can not be identified by reverse engineering. Another example is the development of a mmWave-variant of 22FDX allowing for operation frequencies typically in the 28-80 GHz regime, but also ranging up to 140 GHz. Characterisation of devices up to 3-4 times the operational frequency, a prerequisite for operation of the devices at these frequencies and showcases in the GHz regime for auto-Radar, 5 G and imaging radar are shown. These are just two examples, how the energy efficient 22FDX-technology at GF is enrichened by specialized variants and applications-specific- features.

Novel devices for security and showcases for mmwave with 22FDXTM

STMicroelectronics has developed a new generation of 40nm CMOS technology with embedded Non Volatile Memory targeted to support advanced Microcontrollers platforms. The presentation will briefly describe the very first implementation done with a standard Flash memory with high density but limited granularity (sector erase). We’ll then detail a second step, with a new NVM cell (eSTMTM) integrating a vertical select transistor to offer density similar to standard flash, but better erase control and granularity, that have been integrated in different IP blocks to suit MCU requirements. A latest step, will then be explained, showing further area reduction, as well as some perspective for generation ahead. From a circuit point of view, General Purpose MCUs done, with the initial technology, include a dual core for optimized performance and pass the 1000 DMips mark, while a derived version, using the optimized eSTMTM NVM cell, offer a 30% power consumption reduction. For secure MCU, 3 main applications have been targeted using the 40nm eSTMTM technology: circuit for contactless payment cards with biometry, harvesting enough energy to support a finger print sensor and verification, a circuit for embedded SIM with large NVM to allow high security loading and storage of virtual SIM cards and finally a combined embedded Secure Element and NFC controller (using the smallest eSTMTM cell) to support contactless applications in mobile phone such as payment, access control… Market for each applications represents hundreds of millions of circuits every year requiring robust, reliable and cost effective eNVM technologies.

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